Editorial Contact:
Sarah Miller for ChipVision Design Systems
ThinkBold Corporate Communications
+1 231.264.8636
sarah@thinkbold.com
ChipVision Design Systems, the company whose award-winning, patented PowerOpt™ solution reduces power consumption by up to 75 percent through system-level optimization, today announced it has enhanced its PowerOpt solution with major advances in system-level power optimization, increased the synthesis speed to up to 10 times that of competitive tools, and broadened its language support for designs written in ANSI C, C++ and SystemC. PowerOpt is the only high-level synthesis tool that optimizes design architectures for low power and enables tradeoffs between power, timing and area at the system level. ChipVision will demonstrate the new version of PowerOpt in Booth #3555 at the Design Automation Conference, July 26-31, 2009, in San Francisco.
Many new innovations in PowerOpt bring significant reductions in power consumption in synthesized designs. These innovations include enhanced loop pipelining with automatic run-out support for automatic pipeline flushing; memory access optimizations; and false path elimination and SDC constraint generation, enabling creation of the lowest-power architectures that can be synthesized to gates using RTL synthesis. New features also include enhanced clock-gating optimization to determine lowest-power configuration on a register-by-register basis, as well as finite state machine (FSM) encoding that minimizes switching activity to reduce power. PowerOpt now operates with a higher degree of automation within a given constraints space, while still preserving the options for precise user control via its powerful constraint mechanism.
In addition, ChipVision has dramatically increased the synthesis speed of PowerOpt in this version, showing runtimes up to 10 times faster than other available tools. Other enhancements are in the areas of synthesis optimizations, supported synthesis schemes, and usability. Several new synthesis optimizations help to minimize latency and resource usage as well as register lifetimes. PowerOpt’s synthesis scheme now supports multiple types of blocking and non-blocking communication channels that even allow the transmission of complex data structures over the channels. New Verilog linting support and various new constraints simplify the integration of the synthesized Verilog into existing RTL design environments.
The new version of PowerOpt now also offers broader support for a range of coding styles for ANSI C, C++ and SystemC designs. This means designers can use advanced C++ features such as classes, inheritance, and template functions, and they gain support for SystemC 2.2.
“These new capabilities in PowerOpt have further advanced the state of the art in power optimization,” said Craig Cochran, VP of marketing and business development for ChipVision. “As the only power-optimizing high-level synthesis tool, PowerOpt has shown significant advantages by addressing power at the system-level before an architecture is determined. Designers in the wireless, graphics, consumer and other power-sensitive segments are showing strong interest in this powerful, unique approach that is winning benchmarks and awards.”
Availability
The new version of PowerOpt will be available later this month.
About PowerOpt
Introduced in April 2008, PowerOpt enables system and semiconductor developers to analyze and optimize energy dissipation at the system level in critical blocks of their design; the software automatically creates RTL code optimized for power, performance and area. This ESL approach results in significant energy and time savings – up to 75 percent reduction in power consumption compared to RTL designed by hand – requiring a fraction of the effort. Since the first version of PowerOpt was introduced last year, benchmarking versus competing high-level synthesis tools and manual RTL design has shown that PowerOpt delivers very competitive timing and area results while reducing power by as much as 75 percent compared to those methods. PowerOpt also has garnered several award honors in this timeframe, including winning the eg3.com Fall 2008 “Editors’ Choice” Award and achieving finalist status for EDN's 2008 Innovation Award and the IEC DesignVision Award.
About ChipVision Design Systems
ChipVision helps semiconductor companies significantly reduce power consumption through its leading system-level EDA software. Its award-winning, patented PowerOpt™ product enables semiconductor developers to accurately analyze power consumption at the system level and automatically achieve power savings of up to 75 percent compared to manual RTL design. The software optimizes for low power while synthesizing ANSI C++ and SystemC code into Verilog RTL designs, automatically producing the lowest-power RTL architecture. The company’s solutions are based on open industry standards such as ANSI C, SystemC, CPF and UPF. ChipVision is headquartered in Oldenburg, Germany, and has offices in Munich and San Jose, Calif. For more information about ChipVision, its products and services, visit www.chipvision.com.
ChipVision is a registered trademark and PowerOpt is a trademark of ChipVision Design Systems. All other trademarks are the property of their respective owners.
Sarah Miller for ChipVision Design Systems
ThinkBold Corporate Communications
+1 231.264.8636
sarah@thinkbold.com
CHIPVISION ENHANCES PowerOpt WITH MAJOR ADVANCEMENTS
IN POWER OPTIMIZATION AND C++/SystemC LANGUAGE SUPPORT
OLDENBURG, Germany and SAN JOSE, Calif. – Jul. 7, 2009IN POWER OPTIMIZATION AND C++/SystemC LANGUAGE SUPPORT
ChipVision Design Systems, the company whose award-winning, patented PowerOpt™ solution reduces power consumption by up to 75 percent through system-level optimization, today announced it has enhanced its PowerOpt solution with major advances in system-level power optimization, increased the synthesis speed to up to 10 times that of competitive tools, and broadened its language support for designs written in ANSI C, C++ and SystemC. PowerOpt is the only high-level synthesis tool that optimizes design architectures for low power and enables tradeoffs between power, timing and area at the system level. ChipVision will demonstrate the new version of PowerOpt in Booth #3555 at the Design Automation Conference, July 26-31, 2009, in San Francisco.
Many new innovations in PowerOpt bring significant reductions in power consumption in synthesized designs. These innovations include enhanced loop pipelining with automatic run-out support for automatic pipeline flushing; memory access optimizations; and false path elimination and SDC constraint generation, enabling creation of the lowest-power architectures that can be synthesized to gates using RTL synthesis. New features also include enhanced clock-gating optimization to determine lowest-power configuration on a register-by-register basis, as well as finite state machine (FSM) encoding that minimizes switching activity to reduce power. PowerOpt now operates with a higher degree of automation within a given constraints space, while still preserving the options for precise user control via its powerful constraint mechanism.
In addition, ChipVision has dramatically increased the synthesis speed of PowerOpt in this version, showing runtimes up to 10 times faster than other available tools. Other enhancements are in the areas of synthesis optimizations, supported synthesis schemes, and usability. Several new synthesis optimizations help to minimize latency and resource usage as well as register lifetimes. PowerOpt’s synthesis scheme now supports multiple types of blocking and non-blocking communication channels that even allow the transmission of complex data structures over the channels. New Verilog linting support and various new constraints simplify the integration of the synthesized Verilog into existing RTL design environments.
The new version of PowerOpt now also offers broader support for a range of coding styles for ANSI C, C++ and SystemC designs. This means designers can use advanced C++ features such as classes, inheritance, and template functions, and they gain support for SystemC 2.2.
“These new capabilities in PowerOpt have further advanced the state of the art in power optimization,” said Craig Cochran, VP of marketing and business development for ChipVision. “As the only power-optimizing high-level synthesis tool, PowerOpt has shown significant advantages by addressing power at the system-level before an architecture is determined. Designers in the wireless, graphics, consumer and other power-sensitive segments are showing strong interest in this powerful, unique approach that is winning benchmarks and awards.”
Availability
The new version of PowerOpt will be available later this month.
About PowerOpt
Introduced in April 2008, PowerOpt enables system and semiconductor developers to analyze and optimize energy dissipation at the system level in critical blocks of their design; the software automatically creates RTL code optimized for power, performance and area. This ESL approach results in significant energy and time savings – up to 75 percent reduction in power consumption compared to RTL designed by hand – requiring a fraction of the effort. Since the first version of PowerOpt was introduced last year, benchmarking versus competing high-level synthesis tools and manual RTL design has shown that PowerOpt delivers very competitive timing and area results while reducing power by as much as 75 percent compared to those methods. PowerOpt also has garnered several award honors in this timeframe, including winning the eg3.com Fall 2008 “Editors’ Choice” Award and achieving finalist status for EDN's 2008 Innovation Award and the IEC DesignVision Award.
About ChipVision Design Systems
ChipVision helps semiconductor companies significantly reduce power consumption through its leading system-level EDA software. Its award-winning, patented PowerOpt™ product enables semiconductor developers to accurately analyze power consumption at the system level and automatically achieve power savings of up to 75 percent compared to manual RTL design. The software optimizes for low power while synthesizing ANSI C++ and SystemC code into Verilog RTL designs, automatically producing the lowest-power RTL architecture. The company’s solutions are based on open industry standards such as ANSI C, SystemC, CPF and UPF. ChipVision is headquartered in Oldenburg, Germany, and has offices in Munich and San Jose, Calif. For more information about ChipVision, its products and services, visit www.chipvision.com.
ChipVision is a registered trademark and PowerOpt is a trademark of ChipVision Design Systems. All other trademarks are the property of their respective owners.