|
 |
Facts
Highlights
- Easily imports source code (SystemC and ANSI-C)
- Performs interactive synthesis
- User controls power, area, and timing trade-offs
- Outputs RT model and synthesis constraints
- Closes the gap between system and implementation models
- Outputs CPF/UPF power constraints
- Provides robust leakage modeling strategy
- Implements technology-driven modeling for process, temperature, voltage variations
Benefits
- Up to 60x faster than lower-level methods
- Greatly reduces development cost for low power applications
- Fast implementation exploration quickly finds optimized architecture
- Energy saving up to 75%
Input Formats
Outputs
- Verilog RTL code, testbenches, and test vectors
- Micro Architecture Specification (micro architecture data sheet)
- Power dissipation of different system parts
- Power dissipation and access statistics of memories
- Script files interfacing to logic synthesis tools
- CPF/UPF constraint format
| |
| |
